`include "add.v"
`timescale 1ns/1ns

module tb_add;

reg [63:0] i_a, i_b;
reg i_c;
wire [63:0] o_s;
wire o_c;

add u_add(
  .i_a(i_a),
  .i_b(i_b),
  .i_c(i_c),
  .o_s(o_s),
  .o_c(o_c)
);

initial begin
  $dumpfile("../dump/tb_add.vcd");
  $dumpvars(0, tb_add);
end

initial begin
  #0 i_a = 64'h0;
     i_b = 64'h0;
     i_c = 1'b0;

  #20 i_a = 64'hffff_ffff_ffff_fffe;
  #20 i_b = 64'h2;
  #20 i_a = 64'hffff_ffff_ffff_ffff;
  #20 i_b = 64'hffff_ffff_ffff_ffff;
  #20 i_c = 1'b1;
  $finish();
end

initial begin
  $monitor($time, " i_a:%d i_b:%d i_c:%d o_c:%d o_s:%d", i_a, i_b, i_c, o_c, o_s);
end

endmodule
